When: Wed, May 10, 2017

Time: 11:00AM PDT | 2:00PM EDT


Where: Online: At your desk
 

Abstract: DDR memory interfaces are becoming increasingly common, and present a unique set of challenges to those designing high-speed embedded systems. 

Join Teledyne LeCroy for this free webinar as we first cover the basics of a DDR interface with a focus on physical-layer test challenges and solutions to common problems. We will then outline the general procedures and considerations for compliance, debug and validation test scenarios. Finally, case studies will illustrate how to apply sophisticated test tools to solve real-life problems. 

Topics covered include: 
• Basics of a DDR interface 
• Types of testing 
• Signals of interest 
• Choice of test equipment 
• Probing, interposers and signal access 
• Read/Write burst separation 
• Measurement best practices 
• Compliance testing procedures 
• Debug and validation setups 
• Getting a full system view 
• Dealing with difficult signal fidelity conditions 
• Tracking down compliance failures 


Presented by Patrick Connally, Technical Marketing Engineer, High Bandwidth Oscilloscopes, Teledyne LeCroy

Cost: Free to attend, registration is required



 

Register for the Webinar

LIVE WEBINAR

Practical DDR Testing:
Compliance, Validation and Debug