When: Weds, May 16, 2018
Time: 10:00AM - 1:00PM (Includes lunch)
2708 Orchard Pkwy #20,
San Jose, CA 95134
We will also look at DDR Memory and physical layer testing: If you’re developing or implementing ECS (Embedded Computer System) or ECU’s or just making sure your design is compliant – this is a great workshop.
Topics also include:
- DDR Spec
- Compliance testing and a checklist for pre-compliance testing.
- Test configurations and best practices for DDR probing to eye pattern formation
- Multiple-scenario DDR eye patterns and jitter
- Commands: How to access the DRAM?
- ECC: How does it work and how to test it?
Who should attend: Who Should attend: Memory design EE’s, Tech’s and Job seekers who want a better understanding of DDR Pitfalls and measurement issues at the physical layer.
Cost: FREE, registration is required to hold your seat.
Presenter: Karthik Radhakrishna
Applications Engineer, Teledyne LeCroy
Register for the Seminar
Eliminate Pitfalls of DDR Memory Testing
PLEASE NOTE: All visitors must provide valid government photo identification prior to gaining access to a Teledyne facility. This can be in the form of a driver's license or passport.