When: Wed., July 11, 2018
Time: 10:00AM - 1:00PM (Includes lunch)


Where: Teledyne LeCroy
765 Sycamore Drive
Milpitas, CA 95035

 

Abstract:
Market Drivers are fueling the exponential growth of Ethernet speeds,  port counts and densities.  The challenge to meet the demands of users and applications, and seamlessly interoperate across the ecosystem requires adaptation and evolution of test and measurement tools and practices.

Specific to Phy Layer Designs, both NRZ and PAM4 link interfaces have expanded to include improved communications schemes (Auto-Negotiation) and adapted corresponding high-speed serial link training and equalization practices.

This Seminar will discuss the impact of High-Speed Ethernet connections on hardware bring-up, and how protocol awareness beginning with initial design, through validation, and in the field after deployment, is a requirement.

 
Cost: FREE, registration is required to hold your seat.



 

Register Here

High-Speed Ethernet Designs and Protocol Analysis

        
 

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