When: Tues, August 28, 2018
Time: 10:00AM - 1:00PM (Includes lunch)
Where:
Hilton Garden Inn Austin North
12400 North IH-35 Building C,
Austin, Texas, 78753
This seminar will cover the DDR spec, case studies, real world problems and how to resolve them. Attendees will be able to do hands on testing of the physical layer - from probe connectivity, device patterns, good vs. bad wave forms, and advanced debugging techniques.
We will also look at DDR Memory and physical layer testing: If you’re developing or implementing ECS (Embedded Computer System) or ECU’s or just making sure your design is compliant – this is a great workshop.
Topics also include:
We will also look at DDR Memory and physical layer testing: If you’re developing or implementing ECS (Embedded Computer System) or ECU’s or just making sure your design is compliant – this is a great workshop.
Topics also include:
- DDR Spec
- Compliance testing and a checklist for pre-compliance testing.
- Test configurations and best practices for DDR probing to eye pattern formation
- Multiple-scenario DDR eye patterns and jitter
- Commands: How to access the DRAM?
- ECC: How does it work and how to test it?
Who should attend: Who Should attend: Memory design EE’s, Tech’s and Job seekers who want a better understanding of DDR Pitfalls and measurement issues at the physical layer.
Cost: FREE, registration is required to hold your seat.
Presenter: Karthik Radhakrishna
Applications Engineer, Teledyne LeCroy
Register for the Seminar
Eliminate Pitfalls of DDR Memory Testing
PLEASE NOTE: All visitors must provide valid government photo identification prior to gaining access to a Teledyne facility. This can be in the form of a driver's license or passport.