Become an Expert in DDR Memory Physical Layer Testing
On-Demand Webinar Series

DDR Debug, Compliance & Validation

Join Teledyne LeCroy for this masterclass webinar series to learn about the basics of DDR testing with oscilloscopes, including common test preparation and challenges, the difference between compliance and debug test tools, and practical tips and techniques to increase your DDR validation efficiency and apply the correct debug tools.

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Part 1: Fundamentals of DDR Memory Physical Layer Testing

In this session, we will provide an overview of DDR interfaces and test challenges. Special attention will be paid to the differences between validation and compliance test requirements, and probing for optimum effectiveness.

Part 2: Beyond DDR Compliance Testing — Using Advanced Debug Tools

In this session we review the latest DDR test requirements and provide practical advice on solving test challenges. We will provide guidance on how to test to the latest JEDEC standards and proper use of debug tools to overcome test and validation challenges.

Part 3: Top Tips and Techniques for Better DDR Probing and Testing

In this session we get specific on how to address real-world probing and connectivity issues that impact DDR3/LPDDR3 and DDR4/LPDDR4 measurement capabilities. We will provide examples of what to do or not do and a pre-compliance test checklist will be reviewed.

Part 4: DDR Debug Scenarios and Virtual Probing

In this session we demonstrate the utility of DDR eye patterns required for testing and debugging DDR3/LPDDR3 and higher speed DDR4/LPDDR4 signals using real-world DDR debug examples and specialized connectivity examples.

Teledyne LeCroy offers a full line of DDR test solutions for system bring-up, debug, performance analysis, and compliance.

Register for all Sessions Here

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