Clock and data jitter is a serious problem in high-speed serial links and other time sensitive circuits. Join Professor Eric Bogatin as he demonstrates approaches to characterize the sensitivity of clock jitter to power rail abnormalities.

In this session we will provide an update on USB4 Version 2.0 electrical validation and compliance testing, the latest tools available, and challenges you might encounter in meeting the timelines of the USB-IF test program.

Host and peripheral integrators often must debug link up and interoperability failures associated with using SOC or Re-timer silicon components from multiple vendors - what is referred to in the USB4 specification as the PHY-Logic and Link Layers. Learn how to use an oscilloscope and protocol analyzer simultaneously to ‘see the whole link’ to speed debugging.

When debugging PCI Express problems, it is important to be able to identify which layer is at fault to be able to find the root cause. This presentation will discuss how to simplify debug of Physical Layer issues that are indicated by Data Link Layer or Transaction Layer events.

This discussion will include Link Equalization (LEQ) testing, as well as PAM4 Bit Error Rate (BER), Symbol Error Rate (SER), and jitter tolerance testing. Forward Error Correction (FEC) and Flow Control Unit (FLIT) mode uncorrectable burst error analysis will also be covered in this presentation.

The shift to PAM4 signaling has introduced a new set of transmitter test requirements when moving to PCI Express® 6.0 from earlier generations. In this session we will describe what’s new, what’s the same as past generations, and how to avoid the most common test pitfalls.