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Join Teledyne LeCroy at DesignCon 2024!

Exhibitor Booth #1249

About Teledyne LeCroy
Teledyne LeCroy is a leading provider of oscilloscopes, protocol analyzers, and related test and measurement solutions that enable companies across a wide range of industries to design and test electronic devices of all types. Founded in 1964, its products help engineers resolve design issues faster and more effectively.


Use promo code SPECIAL24 to get a free expo pass and/or 15% off all conference passes.

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DesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley.

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DATE:
January 30 – February 1, 2024

LOCATION:
Santa Clara Convention Center
5001 Great America Pkwy
Santa Clara, CA 95054
Floor Map

Expo Hall Demos (Jan 31- Feb 1)

USB-C Cross Layer Testing

PCI Express 6.0 Cross Layer Testing

Thunderbolt5 / USB4v2 / DP2.1 PHY Compliance

PCIe 7.0 Electrical Transmitter Testing

DDR5 Validation and Compliance Testing

USB & HDMI Cable TestingPCIe Fixture Characterization

Teledyne Storm Microwave

Ethernet and Fibre Channel Test Solutions

Technical Talks by Teledyne LeCroy

Date Event Type Time Room Title
Tue,  Jan 30 Boot Camp 9:00 AM - 4:30 PM Ballroom E Boot Camp – Low-Cost Tools for SI & PI Explorations
Wed, Jan 31 Chiphead Theater  11:15 AM - 12:00 PM Chiphead Theater What is the Bandwidth of Your 10x Probe?
Wed, Jan 31 Technical Session 2:00 PM - 2:45 PM Ballroom B In-Situ Multilayer Printed Circuit Board Characterization Using One-Port Measurements
Wed, Jan 31 Sponsored Session 2:15 PM - 3:00 PM Great America Ballroom 3 Thunderbolt™ 5, USB4® Version 2.0, DisplayPort™ 2.1, USB 3.2 – Latest in Signal Integrity and Tx/Rx Compliance Test Methods for all things USB Type-C®
Wed, Jan 31 Technical Session 3:00 PM - 3:45 PM Ballroom C Compensating Instrument Noise for Eye-Diagram Measurements & Display
Thu, Feb 1 Technical Session 9:00 AM - 9:45 AM Ballroom B Correlation methodology for 128GT/s Operation for PCIe Gen7 DSP based IBIS-AMI models
Thu, Feb 1 Technical Session 12:15 PM - 1:00 PM Ballroom B PAM-4 Signals Testing Considerations: Learnings from PCIe and Ethernet/OIF-CEI for 100+ Gb/s per Lane
Thu, Feb 1 Technical Session 3:00 PM - 3:45 PM Ballroom A Simulation and Measurement Correlation of a Transparent PCIe Gen6 Design

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