PCI Express has used a layered architecture since its inception, which allows a separation of the physical interconnect from the higher layer protocols.
When debugging PCI Express problems, it is important to be able to identify which layer is at fault to be able to find the root cause. PCI Express 4.0 and 5.0 support several new features in addition to the 16 and 32GT/s data rate support, including Lane Margining and Scaled Flow Control. This presents new challenges for developers during bring up and validation.
This presentation will discuss techniques applicable to testing Link Training and Protocol for all PCI Express devices, including those designed to the PCI Express 4.0 and the latest PCI Express 5.0 specification.
Presenter: Gordon Getty, Teledyne LeCroy
Can't attend live? Register anyway and we will send you the recording and slides afterward.
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