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Teledyne LeCroy Seminar

Live Webinar:
DDR Debugging and Best Practice

Date: Tues., Oct 13, 2020
Time: 3PM CEST

Whether you are designing or you simply need to make sure the DDR on your board are working well, this will be an interesting webinar for you to join.

The most difficult part of DDR debugging is probing, and we will make suggestions about probing at the right point, and what you can do when this is not possible. This is the 3rd part of the series of webinar about probing. In the first session we explained what to expect from passive probes, and then which probes to use on various applications. The 4th and last part will cover interposer de-embedding.

Topics to be covered in this webinar:

• Which signals we need for DDR/LPDDR debugging and for compliance test
• We will explain how we can separate Read and Write bursts
• Where probes should be soldered
• We will show signal captured and what happens when probes are not soldered in the correct place
• How to remove reflection
• Setup and execute a full compliance test with an example on DDR3

DDR debugging and best practice Webinar

Requirements: Signal integrity background and understanding of high-speed serial data.

Who should attend: HW and test engineers involved with DDR/LPDDR debugging and testing

You will learn which probes to use, how to probe DDR and avoid common mistakes

Presenter: Maurizio Mastrofini, Teledyne LeCroy

Can't attend live? Register anyway and we will send you the recording and slides afterward.

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