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Teledyne LeCroy Seminar

Live Webinar:
DDR/LPDDRD Debugging and Compliance Tests

Date: Tues., Mar 09, 2021
Time: 3PM CET

A new board is almost ready to be verified; the first step is to make sure the memory is working as expected. You have 2 steps, first debug and then validate the memory implementation, let’s review all this together and find out how to avoid common mistakes.

This is the 2rd part of the series of webinar about DDR. In the first session we explained how to connect probes for DDR testing at the right point; we explained a simple method to remove reflections caused by improper terminations and by probing far from the desired point. During this session we will go a bit further, first we will review how to use DDR debugging tool, how to set up QPHY for a compliance test and then how to de-embed an interposer.

Topics to be covered in this webinar:
• Which signals we need for DDR/LPDDR debugging and for compliance test
• We will explain how Read and Write bursts can be identified and separated
• DDR debugging tool: before running a full DDR validation let’s see if everything is setup correctly
• Remove the effect of the interpose, using our passive circuit simulator
• Use what we have learned with DDR debugging tool to setup a full compliance test

DDR debugging and best practice Webinar

Requirements: Familiarity with DDR signals and requirements, signal integrity basic knowledge.

Who should attend: HW and test engineers involved with DDR/LPDDR debugging and testing

You will learn how to debug DDR signals, remove reflections, the effect of an interposer and how to setup the DDR compliance test.

Presenter: Maurizio Mastrofini, Teledyne LeCroy
Can't attend live? Register anyway and we will send you the recording and slides afterward.

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