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The Impact of Power Rail Noise
on Clock Jitter

Date: Wed, April 28, 2021
Time: 11AM Pacific | 2PM Eastern
Duration: 60 minutes

The Impact of Power Rail Noise on Clock Jitter Webinar

Noise on the power rail may not only create bit errors due to voltage spikes, but it may also increase clock jitter. Clock jitter is an insidious source of noise difficult to debug.

In this webinar, we demonstrate how to measure the jitter in both clocks and data and identify the contribution from noise on the power rail. These techniques can be applied to any system in which minimizing clock and data jitter is important.

Topics to be covered in this webinar:

  • Using time interval error (TIE) to measure jitter
  • The statistics and spectrum of TIE as a way of characterizing jitter
  • Typical jitter in various types of oscillator circuits
  • Best practices to measure power rail noise
  • The impact power noise can have on clock jitter
  • Examples of clocked systems with high and low jitter sensitivity to power rail noise

Who should attend? Hardware and circuit engineers who design interconnects and clocked circuits.

What attendees will learn? This webinar will introduce you to how to measure jitter and power rail noise, and how to reduce the sensitivity of your clocks to power rail noise.

Presenter: Dr. Eric Bogatin, Teledyne LeCroy Fellow


Can't attend live? Register anyway, and we will send you the recording and slides afterward.

By ticking this box you agree to receive information from Teledyne and our authorized sales representatives and distributors about our latest news, events and products and/or services by email. Please see our privacy policy at http://www.teledyne.com/privacy-policy

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