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Practical On-die Power Integrity Measurements

Part 8: How to Become an Expert in Power Integrity Testing

Practical On-die Power Integrity Measurements Webinar

AVAILABLE ON-DEMAND

How to Become an Expert in Power Integrity Testing Webinar Series
Power Distribution Networks (PDNs) require careful design to ensure excellent power integrity, especially in high-speed designs. This 8-part series walks you through the fundamentals to advanced topics with a large number of live demonstrations. Click here to access the entire series.

Practical On-die Power Integrity Measurements
In this session (Part 8), Dr. Eric Bogatin will describe the direct measurement of power rail noise on the chip itself (i.e. on die). One goal of PDN design is to engineer the power delivery network to deliver low noise DC voltages to the power rails on the die. The final test of the power noise is measuring the on-die power rail noise directly. Using a simple technique, we can directly measure the on-die power rail noise for the VCC rails, and if we plan ahead of time, sometimes the Vdd rails. Eric will introduce the method and look at two examples of measuring the on-die power noise and how some of the important design features affect this noise.

Topics to be covered in this webinar:

What is the origin of power rail collapse
Measuring rail collapse on die and on the board
Measuring rail compression
Impact from decoupling capacitor location on rail collapse and compression
Noise on die when the board is the aggressor

Who should attend? Hardware design and validation engineers and signal/power integrity engineers interested involved in designing any aspect of the PDN.

What attendees will learn? The root cause of one type of PDN noise will be revealed and some design techniques to avoid this. Most importantly, you will learn how to measure the noise on the die and how different it is from the board level noise.

Presenter: Dr. Eric Bogatin, Teledyne LeCroy Fellow

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