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Webinar:
Fundamentals of DDR Memory Physical Layer Validation, Debug and Compliance Test

Date: Wed. 29 Sept 2021
Time: 15:00 CEST

Fundamentals of DDR Memory Physical Layer Testing Webinar

In this session we will provide an overview of DDR interfaces and test challenges. Special attention will be paid to the differences between validation and compliance test requirements, and probing for optimum effectiveness.

Topics to be included:

Basics of DDR testing
Common DDR test challenges
Preparing for physical layer testing
DDR compliance testing overview
DDR validation and debug overview

Who should attend? Design and validation engineers working to validate and debug DDR in embedded systems.

What attendees will learn? DDR interface basics, the differences between compliance and debug, and best and most efficient practices for DDR probing and test.

Presenter: Dr. Patrick Connally, Product Marketing Manager

Can't attend live? Register anyway and we will send you the recording and slides afterward.

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