Date: Tuesday, 15 March 2022
Time: 16:00 CET
Join Teledyne LeCroy as we describe and demonstrate best practices for de-embedding interconnect elements. The ability to carry out de-embedding using a combination of different techniques is a key element in improving the accuracy of the obtained S-parameters. The use of TDR, which allows for accurate measurement of characteristic impedance as well as electrical length, allows for an extension of the techniques used, while at the same time increasing their accuracy
Topics to be covered in this webinar:
- Why de-embedding is almost always necessary
- Best practices for reference-plane calibration
- Traditional frequency-domain and time-domain (gating, peeling, fixture removal) de-embedding
- De-embedding by comparison (2xThru, Delta-L…)
- How TDR provides accurate impedance profile measurements and enforces causality conditions feared by VNA.
Who should attend? Hardware engineers who use a Vector Network Analyzer (VNA) to obtain S-parameters for high-speed interconnects
What attendees will learn: Hardware engineers who use a Vector Network Analyzer (VNA) to obtain S-parameters for high-speed interconnects
Presenter: Giuseppe Leccia, High-speed Interconnects Analysis, Teledyne LeCroy
Can't attend live? Register anyway and we will send you the recording and slides afterwards.