Lorem ipsum dolor sit amet, consectetur adipiscing elit. Duis a risus facilisis, molestie ipsum vel, tempus metus. Donec eu porttitor nunc. Nullam dictum magna at sapien convallis varius. Vivamus feugiat, purus eget mollis sagittis, metus ligula faucibus magna, ac tincidunt sem arcu at nibh. Fusce eu commodo dui. Quisque dolor nulla, ornare vitae pretium vitae, facilisis in leo. Ut facilisis suscipit leo et ultricies. Aliquam id urna porttitor, varius libero in, malesuada purus.
Q: If i have a double sided PCB, it is better to place decoupling capacitors on the back of the PCB under the device or on the top side near the power pin.
A: In a 2-layer board. Always better to use the top surface for the caps and keep them close to the IC power pins, with shor twide traces. This is usually the lowest inductance path.
Q: How's "Return via" defined on this 4-layer board? Thanks.
A: A return via is a via that shorts the two ground planes. It is a through hole via.
Q: You showed that it was better to put two ground planes in the middle of a four layer board. Why not just have one ground plane instead of two.
A: One ground plane will work, just be careful to keep the two signal layers tha tuse the same ground plane to be routed orthogonal. This will prevent the cross talk between these two layers.
Q: How close we need to put scope probe to measure die noise?
"
A: Proximity is not important. The interconnect from the IC I/O pad to the scope probe is a transmission line, so the noise propagates like a signal would. But, any additional length of the sense line is a source of additional cross talk noise you will pick up.
Q: In case of multiple GND planes (AGND and PGND) recommended in switching regs and connected at a single point, what would be optimal method to avoid crosstalk and noise to plague the sensitive signal components?
A: Usually no need for separate AGND and PGND unless you are driving > 50 A. Then keep the PGND isolated from the AGND. Use the AGND plane for all return currents of signals.
Q: Great talk, thanks Eric! I'd love to get my hands on a copy of Principles of Power Integrity for PDN Design, but the publisher says it's out of print. Do you know if another print run is planned?
A: Try the soft copy.
Q: I note that bandwidth limiting (BwL) is enabled on the scope channels. What is the BW limit?
A: Good eye! I had forgotten I had this set on the two channels when I did this measurement. I was using ti to filter out some 2.5 GHz wiFi signals in my previous measurement that was getting picked up on some probes. In any event the 10x probes were filtering probably to 300 MHz so the use of the BW limit probably had no effect on the measurements.
Q: It would be great to have a test point at the package pin or decoupling caps on the board to see the effect of your board PDN that long thin trace for the power supply from the VRM to the hex inverter.
A: Designing in a test point to look on the power rail or the package lead is always a good idea, but it will never give yo uthe voltage on the die due to the loop inductance from the die pad to the board pad. This is why an on-die measurement is so important.
Q: Do you have a general preference of using a GND polygon on top and bottom layers and using via stitching?
A: No need for a ground polygone or ground pour on top and bottom layers. What problem is this solving?
Q: Putting in numbers: what's a general rule for the switching noise level in mV
for a non crytiical project?
A: Very tough to estimate, but I cover this in my text book and in the EPSI online lectures. Use the dI/dt currents and estiamt ethe total inductance of the return path.
Q: Have you also run a test board comparing signals running from L1 to L3 with L2 reference to compare to L1 with no plane changes?
A: No. But, you should not have much ground boucne in the signal vias when going from L1 to L3, as long as you don’t have much return current on the L4 layer.
Q: Thanks a lot for your valuable presentation; one of the famous policies on the PCB design procedure is increasing the area of ground, this technique can help to reduce the inductance of the return path?
A: I have not heard this recommendation. It is far better to use a continuous ground plane, rather than a shared ground and signal layer.
Q: If there are 2 decoupling caps, say 1uF and 0.1uF, keeping 0.1uF next to IC power pin and 1uF next to 0.1uF and then via to the power plane - or should we have vias from each of the caps?
A: Why do you have 2 different value capacitors? If you want low inductance, better to keep the smaller body size cap closer to the IC pads. Do everything to make low inductance.
Q:I thought it's good to have power plane close to ground plane, to have better plane capacitance and have a good return from power to ground. But you mentioned to have two ground planes next to each other to be able to short them. How to balance that?
A: It is not necessary to use a power plane. Most important is to have low loop inductance between the decoupling capacitor and the IC pins. Can do this with a "power puddle" on the signal layer.
Q:If we bring the signal closer to the GND plane, do we need to worry about increasing the capacitance and having signal loss or LPF effects through that capacitance?
A: Yes, as the signal is brought closer to the gnd plane, the interconnect impedance will decrease. You will have to balance this tradeoff.
Q: In boards that have ASICs in them, power planes are usually in the middle of the stackup. In order to tie all GND planes together, these power planes need to have GND shapes in them too. Are there any rules of thumb for how far does the power shape need to be from the GND shape in order to not couple switching noise to the GND planes?
A: To tie all the gnd planes together, you need clearance holes through the power planes. Always try to use the ground planes as the return paths.
Q: Our std. boards are 12-14 layers. We typically have signal layers on the outer layers followed by GND planes on layer 2 and 11. Then another signal layer on 3 and 10. Layers 4 and 9 are GND then we bury the split or solid power planes between these solid GND layers. What happens to return currents in that center chunk of the board. Note, all GND layers are stitched together.
A: Excellent stack up. The return currents will never see the burried split power plane. Just use shorting vias between all the ground planes where ever a signal via has a via.
Q: How does the proximity of the plane affect the ground bounce? if the stackup has sig/gnd/pwr/sig/sig/pwr/gnd/sig so two layers in the middle have a greater distance to the reference (gnd) plane
A: The closer the signal layer is to the plane, the large the fraction of the return current will be in that plane. If you keep a return plane at least 4x away from the signal line compared to the other plane, little return current will flow in it.
Q: What's the height from your top trace to the plane & return trace. (slide 14 bounce test example)
A: This board is 60 mils thick for all the 2-layer boards.
Q: It looks like in the first set of examples, you had no power plane connection to the decoupling capacitors, just a trace. Is this correct? Does position matter much if there is a power plane?
A: Yes, correct. The connection between the cap pads and the IC was on a signal layer. It was kept short and wide.
Q: Would be noise much bigger if only every second via would be present?
(in last example)
A: Yes. The fewer the return vias, the more the noise. It is difficult to estiamte, but there 1 return vai per 2 signals, may be sufficient to keep the noise low enough. This is a difficult tradeoff to analyze wtihout using a tool like Siwave or Sipro.
Q: Are the return vias for a signal trace connected to ground? I just wanted to clarify because I was confused for a portion of the seminar. For the section where you talked about 4-layer boards, the labeling ""G"" and ""P"" gave me the impression that the ""2nd"" and ""3rd"" layer on the 4 layer board you talked about was the ground and power plain, respectively.
For 2 layer boards, I assume ground vias close to signal traces would apply in a similar fashion as well?
A: Yes, a return via is connected between two ground planes. In this example of the 4-layer board, the P plane was acutally just floating to illustrate the problem having a floatin gor high impedance plane causes as a return plane.
Q: If the rail collapse is significant enough in an IC that includes a supervisory circuit, could it trip the reset circuit?
A: Yes, absolutely!
Q: Placing local decoupling capacitors close to the Vcc/Vdd pin(s) of the IC using wide traces makes sense. But, for small SMD capacitors, is it ok to "neck down" the trace segments as they approach the capacitor pads?
A: Yes. All designs have a tradeoff. Shorter is better than wider.
Q: Will return currents flow in adjacent signals?
A: Only a little. This is from the mutual inductance coupling between two loop, always less than the shared return path coupling of a common return path.
Q: What if decap is closer to pin but gnd connection to decoupling cap is longer? especially in case where decaps for bga component are kept on bottom , 10 layers apart
A: Yes, you are correct. It is the loop inductance that is important to keep small as possible.
"This is fantastic! Thanks so much guys!"
"This template is amazing. I've been using it to create lots of super nice landing pages."
"Thanks so much for making this template available to us!"
This landing page will look great on any device, no matter the size!
Use Bootstrap grid, classes, and utilities.
Easy to change colors, padding, content, order, and more.
Ready to add your styles and content!
Lorem ipsum dolor sit amet, consectetur adipiscing elit. Duis a risus facilisis, molestie ipsum vel, tempus metus. Donec eu porttitor nunc. Nullam dictum magna at sapien convallis varius. Vivamus feugiat, purus eget mollis sagittis, metus ligula faucibus magna
see moreLorem ipsum dolor sit amet, consectetur adipiscing elit. Duis a risus facilisis, molestie ipsum vel, tempus metus. Donec eu porttitor nunc. Nullam dictum magna at sapien convallis varius. Vivamus feugiat, purus eget mollis sagittis, metus ligula faucibus magna, ac tincidunt sem arcu at nibh. Fusce eu commodo dui. Quisque dolor nulla, ornare vitae pretium vitae, facilisis in leo. Ut facilisis suscipit leo et ultricies. Aliquam id urna porttitor, varius libero in, malesuada purus.
