How to Debug USB4® PHY-logic and Sideband Link Layers

Debug and validate active link behavior across electrical and protocol layers


This webinar was originally held on March 1, 2023.

How to Debug USB4® PHY-logic and Sideband Link Layers

Have you thought about using an oscilloscope and a protocol analyzer together to debug USB system level interoperability failures? Host and peripheral integrators often must debug link up and interoperability failures associated with using SOC or Re-timer silicon components from multiple vendors - what is referred to in the USB4® specification as the PHY-Logic and Link Layers. Using an oscilloscope and protocol analyzer simultaneously to ‘see the whole link’ is the ideal way to speed debugging.

Topics to be covered in this webinar:

  • How to probe the signal without impacting system performance
  • The importance of triggering on sideband and protocol packets
  • Synchronizing all the information in one total view

Who should attend? System Engineers, Firmware Engineers, and USB IC Field Support Engineers.

What attendees will learn? Practical methods for uncovering compliance and interoperability issues using an oscilloscope.

Presented by:
Mike Engbretson, Product Marketing Manager
Mike Micheletti, Senior Product Marketing Manager

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