Date: Wednesday, 05 July 2023
Time: 15:00 CET
In this webinar we will provide an overview of DDR interfaces and test challenges. Special attention will be paid to the differences between validation and compliance test requirements, and probing for optimum effectiveness.
Topics to be included:
- Basics of DDR testing
- Common DDR test challenges
- Preparing for physical layer testing
- DDR compliance testing overview
- DDR validation and debug overview
Who should attend? Design and validation engineers working to validate and debug DDR in embedded systems.
What attendees will learn? DDR interface basics, the differences between compliance and debug, and best and most efficient practices for DDR probing and test.
Presenter: Maurizio Mastrofini, Teledyne LeCroy
Can't attend live? Register anyway and we will send you the recording afterward.