DDR Technology
How to Probe and Debug DDR Signals

DDR Probing Webinar

Date: Tuesday, 26 September 2023
Time: 10:00 CEST

 

DDR memories are constantly increasing their speed and technicians need advanced tools to validate and debug their system.

We will review the basics of DDR and the common DDR challenges, including probing, showing how to solve them by choosing the right measurement tools and setting the scope for best results.

A case study will be presented to explain how to validate and debug a DDR memory.

Topics to be covered in this webinar:

  • Basics of DDR testing
    • Basics of a DDR interface
    • Types of testing
    • Signals of interest
  • Common DDR test challenges
    • Signal access
    • Burst separation
  • Preparing for physical layer testing
    • Choosing test equipment
    • Optimizing oscilloscope setup
  • DDR validation and debug
    • Case study – tracking down a potential signal fidelity issue

 

Presenter: Giulio Fabbro, EMEA High Speed Serial Data BDM, Teledyne LeCroy

Can't attend live? Register anyway and we will send you the recording and slides afterwards.

By ticking this box you agree to receive information from Teledyne and our authorized sales representatives and distributors about our latest news, events and products and/or services by email. Please see our privacy policy at http://www.teledyne.com/privacy-policy