Join Teledyne LeCroy for this 4-part webinar to learn about physical layer DDR memory testing, from basic fundamentals through JEDEC DDR PHY compliance test, practical tips and techniques to increase your DDR debug skills and DDR validation efficiency, and the latest changes required for DDR5 memory test, including DDR eye diagrams and jitter measurements. Each webinar will run about 60 minutes and include a live Q&A.
Part 1: Fundamentals of DDR Memory Testing
Presenter: Sriram Venkatesha, Product Manager
Date: Wednesday, September 25, 2024
Time: 11:00AM Pacific | 2:00PM Eastern
In this webinar, we'll be offering a comprehensive introduction to DDR interfaces along with the challenges encountered during testing. We will focus particularly on distinguishing between validation and compliance testing requirements, as well as preparing for DDR memory testing.
Part 2: Tips and Techniques for DDR Probing
Presenter: Mike Hertz, Senior Field Applications Engineer
Date: Wednesday, October 9, 2024
Time: 11:00AM Pacific | 2:00PM Eastern
In this webinar, we get specific on how to address real-world probing and connectivity issues that impact DDR measurement capabilities. We will provide examples of what to do or not do and a pre-compliance test checklist will be reviewed.
Part 3: DDR Debug and Virtual Probing
Presenter: Mike Hertz, Senior Field Applications Engineer
Date: October 30, 2024
Time: 11:00AM Pacific | 2:00PM Eastern
In this webinar, we provide practical advice on overcoming DDR test challenges using debug tools. Topics include real-world DDR debugging examples like logic, soldering, and power supply issues, DDR read/write separation, eye pattern formation, and addressing missing clock cycles. We'll also discuss DDR eye patterns, jitter in multiple scenarios, hardware-based read-write separation, and virtual probing techniques.
Part 4: What’s New with DDR5 Memory Testing
Presenter: Sriram Venkatesha, Product Manager
Date: Wednesday, November 20, 2024
Time: 11:00AM Pacific | 2:00PM Eastern
We will we provide details on how the JEDEC DDR5 and LPDDR5 specification and test requirements are different from previous versions of DDR, and how you can optimize your DDR5 and LPDDR5 memory testing.