How to Debug DisplayPort™ 2.1 PHY-logic
and Sideband Link Layers

How to Debug DisplayPort™ 2.0 PHY-logic and Sideband Link Layers Webinar

AVAILABLE ON-DEMAND

This webinar was originally held on September 11, 2024.

How to Debug DisplayPort 2.1 PHY-logic and Sideband Link Layers

This webinar tackles common issues that arise when connecting USB-C devices and ensures they work together smoothly (compliance and interoperability). We'll show you practical debugging techniques to fix electrical problems and make sure your devices meet all VESA specifications.

Topics to be covered in this webinar:

  • What happens when you attach the USB-C cable?
  • Probing at compliance test points (TP2, TP3)
  • Debugging Power Delivery (USB-PD) and Alt-Mode Issues
  • Debugging main link and AUX linkup issues

Who should attend? System Engineers, Firmware Engineers, and USB IC Field Support Engineers.

What attendees will learn:  Practical methods for uncovering compliance and interoperability issues using an oscilloscope.

Presenters: 
Mike Engbretson, Teledyne LeCroy Product Marketing Manager

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