Date: Wednesday, April 30, 2025
Time: 11:00 AM Pacific | 2:00 PM Eastern
Duration: 60 mins including live Q&A
This webinar is an overview and Q&A session of the Whitepaper of the same name authored by the presenters. Please download the whitepaper prior to registering for this webinar event to get the most out of this live session.
Your USB4® and DisplayPort™ Designs Will Fail Unless You Understand Link Training
Consumers are increasingly frustrated with USB Type-C ports not operating as specified or having intermittent link failure issues. If your designs pass compliance test but fails at interoperability workshops then you need to learn more about link training debug – The recent introduction of retimers into system designs has increased the number of issues seen by product integrators.
Topics to be covered in this webinar:
- What function does a retimer or LTTPR perform?
- Why do these problems exist with USB4 but not USB 3.2?
- What are the differences in SoC and retimer designs amongst vendors?
- Practical synchronous capture test setup for debug
- Introduction to cross-layer analysis (physical and link layer)
- Real-world debug examples
Who should attend? System, firmware and signal integrity engineers designing and testing USB4 and DisplayPort links and devices.
What will attendees learn? Why products pass compliance but fail interoperability, and how to apply new debug techniques to learn the root cause of interoperability failures.
Presented by: Mike Engbretson, Product Marketing Manager, Teledyne LeCroy
Giulio Fabbro, High-speed Serial Data Specialist, EMEA, Teledyne LeCroy
Matthew Neighbour, Senior Hardware Applications Engineer, Kandou
Can't join us live? Register now and receive the recording later.