Date: Tuesday, April 21, 2026
Time: 10:00 AM - 2:00 PM, Includes Lunch
Cost: Registration is now Closed. Contact hilary.lustig@teledyne.com for more information
Location: Teledyne LeCroy 765 Sycamore Drive, Milpitas, CA 95035
Join technical experts from Teledyne LeCroy and Anritsu for an in‑person seminar focused on understanding, validating, and debugging PCI Express technologies from PCIe 5.0 through PCIe 6.x, with a look ahead to PCIe 7.0. Doors open at 9:30 AM, and the presentation will begin promptly at 10:00 AM.
PCI Express Architecture and Evolution
In this session we discuss a brief history of PCI Express, its importance in today’s exploding data center build out and artificial intelligence ecosystem. The PCI Express 6.x specifications enable many new capabilities including the 64GT/s data rate using PAM4 signaling which also carry over into the new PCIe 7.0, 128GT/s specification. These changes require significant changes to the protocol layers to support the new signaling. This seminar will discuss changes to Link Training including Equalization protocol, and also the changes to the Data Link Layer and Transaction Layer when the link is operating in both Flit mode and Non-Flit mode. The presentation will also discuss key techniques to assist in analyzing, troubleshooting and debugging systems and endpoints designed to the PCIe 6.0 specification.
Debugging a PCI Express at 32GT/s NRZ and 64GT/s PAM4 speeds
In this session we provide an overview of common validation test challenges as part of system functional testing, including how to measure substate timing events and measure substate power consumption. The attendee will learn about a novel approach for debugging a PCI Express link using live traffic. We incorporate the use of both a Protocol Analyzer, Real Time Oscilloscope and Cross Layer Software tools to expose both the protocol and electrical layers to the user in a time correlated view that provides superior insight into the behavior of a live PCIe link.
Compliance Testing of PCIe 6.0 Hosts and Devices and Current PCIe 7.0 Capability
In this session we provide a review of the Electrical and Protocol Layer BASE and CEM compliance testing. We will review the instruments, the test fixtures, and the software components that are needed to perform successful electrical and protocol testing. This includes Transmitter Test, Receiver Calibration and Receiver LEQ Testing. We will review how to successfully characterize PCIe Test Fixtures and provide the best practices for a successful stressed eye calibration. The attendees will learn all aspects of the setup and the test methodology as per the PCI-SIG and PCIe Specifications (BASE and CEM). In addition we will provide information of our PCIe 7.0 testing and how it is similar and different relative to PCIe 6.0. This session is a must see for anyone working in PCIe, especially those involved in device design, validation, compliance or testing.
Presenters:
Teledyne LeCroy
Gordon Getty - Director of Product Management, Protocol Test Solutions
Michael Baker - Technical Sales Engineer, High Speed Serial Data Test Solutions
Anritsu
Robert Luo - Senior Field Applications Engineer