Date: Wednesday, July 22, 2026
Time: 11 AM Pacific | 2 PM Eastern
Duration: 60 minutes
How to Measure Jitter Induced by PDN Noise
Join Teledyne LeCroy and Professor Eric Bogatin as he discusses and demonstrates how to measure in-circuit jitter caused by PDN power integrity noise and other abnormalities. Clock and data jitter is a serious problem in high-speed serial links and other time sensitive circuits, and we will demonstrate approaches to characterize the sensitivity of clock jitter to power rail abnormalities.
Topics to be covered in this webinar:
- Best practices for measuring power rails
- Correlating jitter to power rail noise and other behaviors
- Inducing well-defined noise signatures on power rails to cause jitter
- Helpful tools to measure and correlate jitter
Who should attend? Hardware design and validation engineers and technicians interested in learning more about PDN noise and power integrity problems and solutions.
What will attendees learn? Attendees will be given a thorough background in power integrity and how to assess it in a design.
Presented by: Eric Bogatin, Teledyne LeCroy Fellow and Professor, ECEE Univ of Colorado, Boulder
Can't join us live? As a registrant, you will receive the recording automatically.