This series from Teledyne LeCroy is designed to take you from the fundamentals of DDR memory testing to advanced DDR PHY compliance, validation, and debug techniques. Across four sessions, you'll learn how to improve DDR validation efficiency, troubleshoot common challenges, and understand the latest DDR5 test requirements, including eye diagram and jitter measurements.
Part 1: Fundamentals of DDR Memory Testing
Now Available On-Demand
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Presenter: Sriram Venkatesha, Product Manager
In this first webinar, we'll introduce DDR interfaces, explore key test challenges, and discuss the differences between validation and compliance testing. You'll also learn how to prepare for successful DDR PHY testing.
Part 2: Tips and Techniques for DDR Probing
Date: Wednesday, September 30, 2026
Time: 11 AM Pacific | 2 PM Eastern
Duration: 60 minutes
Presenter: Mike Hertz, Senior Field Applications Engineer
In this webinar, we get specific on how to address real-world probing and connectivity issues that impact DDR measurement capabilities. We will provide examples of what to do or not do and a pre-compliance test checklist will be reviewed.
Part 3: DDR Debug and Virtual Probing
Date: Wednesday, October 7, 2026
Time: 11 AM Pacific | 2 PM Eastern
Duration: 60 minutes
Presenter: Mike Hertz, Senior Field Applications Engineer
In this webinar, we provide practical advice on overcoming DDR test challenges using debug tools. Topics include real-world DDR debugging examples like logic, soldering, and power supply issues, DDR read/write separation, eye pattern formation, and addressing missing clock cycles. We'll also discuss DDR eye patterns, jitter in multiple scenarios, hardware-based read-write separation, and virtual probing techniques.
Part 4: What’s New with DDR5 Memory Testing
Date: Wednesday, October 14, 2026
Time: 11 AM Pacific | 2 PM Eastern
Duration: 60 minutes
Presenter: Sriram Venkatesha, Product Manager
We will we provide details on how the JEDEC DDR5 and LPDDR5 specification and test requirements are different from previous versions of DDR, and how you can optimize your DDR5 and LPDDR5 memory testing.
Who should attend?
Designed for hardware design, validation, and test engineers who want to improve their DDR measurement skills, accelerate debug, and gain confidence in DDR compliance and validation testing.
What will attendees learn?
From DDR fundamentals to probing, debug, and DDR5 validation techniques, attendees will learn practical measurement strategies and best practices that improve testing accuracy and efficiency.
Can't attend live? Register anyway and receive the recording when it's available.