/* HOW TO USE: Change "display: inherit;" to "display: none;" to hide a section. Change the "order" property to change the order a section appears on the page. Sections with lowest order will appear first. EG 1, 2, 3, 5, 10 E.G. The hero section below will be visible and will be displayed third. #hero { display: inherit; order: 3; } The video section will be hidden so the order property for this section is ignored. #video { display: none; order: 5; } Hex code cheat sheet: Blue: #0076c0 Light Gray: #f3f3f3 Default Text Color: #222222 */ #fluid { background-color: #ffffff; display: none; order: 1; } #hero { background: url("https://placehold.it/3840x2458") no-repeat center center; display: none; order: 2; padding-bottom: 192px; padding-top: 192px; } /* Change hero overlay background-color to change the color on top of the hero image Opacity changes the transparency-level: 1 is not transparent at all, 0.5 is 50% see-through, and 0 is completely transparent */ #hero .overlay { background-color: #222222; opacity: 0.3; } #headline { background-color: #ffffff; display: none; order: 3; } #C6733 { background-color: #ffffff; display: inherit; order: 4; } #C2 { background-color: #ffffff; display: none; order: 5; } #C3 { background-color: #ffffff; display: none; order: 6; } #C4 { background-color: #ffffff; display: none; order: 7; } #C3367 { background-color: #f3f3f3; display: none; order: 8; } #form { background-color: #ffffff; display: none; order: 9; } #full-width-text { background-color: #ffffff; display: none; order: 10; } #video { background-color: #f3f3f3; display: none; order: 11; }

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June 12 Webinar - Oscilloscope Basics
Focus On: Debugging Embedded Systems

How to Accelerate and Improve 16+ Gb/s Serial Data Transmitter/Receiver Test and Debug

Identifying and Debugging PCIe® Link Equalization Problems
On Demand Webinar

REGISTER TO ACCESS RECORDING

Identifying and Debugging PCIe Link Equalization Problems

Join Teledyne LeCroy for our new three-part webinar series to learn more about how to accelerate and improve testing of PCIe® v. 4.0 and 5.0, USB4™, Thunderbolt™ 4, and DisplayPort™ 2.0 serial data links.

Nov. 19 - Part One: Identifying and Debugging PCIe Link Equalization Problems
Dec. 3 - Part Two: Simplifying Receiver Calibration and Test of 16+ Gb/s Serial Data Links
Dec. 16 - Part Three: Optimizing Transmitter Test and Margin Analysis of 16+ Gb/s Signals

Join us for Part One – Identifying and Debugging PCIe Link Equalization Problems

Verifying link performance requires identification of potential signal integrity issues during the link equalization and training phase of a link negotiation. Link negotiation occurs at multiple layers within the PCIe layered architecture. This presents unique test challenges that require simultaneous views of both the physical and protocol (data link and transaction) layers.

This webinar will demonstrate how to identify and debug potential signal integrity issues that may lead to poor link performance.

Who should attend?

Signal Integrity Engineers
Design and Validation Test Engineers
Firmware Test Engineers

What attendees will learn?
Attendees will learn how to efficiently identify and quickly debug PCIe Link Training problems that may arise from potential signal integrity issues.

Presenters:
Dr. Patrick Connally, Product Marketing Manager and John Smith, HSS Business Development Manager

Click here for details on Part Two

Click here for details on Part Three

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