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Fundamentals of DDR Memory Physical Layer Testing

Part 1: Become an Expert in DDR Memory Physical Layer Testing Webinar Series

NOW AVAILABLE ON DEMAND

This webinar was originally held on February 11, 2021.

Watch the rest of the series:

Part Two: Beyond DDR Compliance Testing — Using Advanced Debug Tools
Part Three: Top Tips and Techniques for Better DDR Probing and Testing
Part Four: DDR Debug Scenarios and Virtual Probing

Fundamentals of DDR Memory Physical Layer Testing Webinar

How to Become an Expert in DDR Memory Physical Layer Testing Series
Join Teledyne LeCroy for this 4-part DDR Memory Master Class to learn about the basics of DDR testing with oscilloscopes, including common test preparation and challenges, the difference between compliance and debug test tools, and practical tips and techniques to increase your DDR validation efficiency and apply the correct debug tools.

Fundamentals of DDR Memory Physical Layer Testing
In this session (Part 1), we will provide an overview of DDR interfaces and test challenges. Special attention will be paid to the differences between validation and compliance test requirements, and probing for optimum effectiveness.

Topics to be included:

Basics of DDR testing
Common DDR test challenges
Preparing for physical layer testing
DDR compliance testing overview
DDR validation and debug overview

Who should attend? Design and validation engineers working to validate and debug DDR in embedded systems.

What attendees will learn? DDR interface basics, the differences between compliance and debug, and best and most efficient practices for DDR probing and test.

Presenter: Dr. Patrick Connally, Product Marketing Manager

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