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Beyond DDR Compliance Testing — Using Advanced Debug Tools

Part Two of Four

Date: Thurs, Mar. 11, 2021
Time: 11AM Pacific | 2PM Eastern
Duration: 1 hour

Beyond DDR Compliance Testing — Using Advanced Debug Tools Webinar

How to Become an Expert in DDR Memory Physical Layer Testing Series
Join Teledyne LeCroy for this 4-part DDR Memory Master Class to learn about the basics of DDR testing with oscilloscopes, including common test preparation and challenges, the difference between compliance and debug test tools, and practical tips and techniques to increase your DDR validation efficiency and apply the correct debug tools.

Beyond DDR Compliance Testing — Using Advanced Debug Tools
In this session (Part 2), we review the latest DDR test requirements and provide practical advice on solving test challenges. We will provide guidance on how to test to the latest JEDEC standards and proper use of debug tools to overcome test and validation challenges.

Topics to be included:

  • DDR/LPDDR4, LPDDR4X, and DDR/LPDDR5 specification review
  • Test system ‘bring-up’ and debug
  • When are you ready to move from ‘debug’ to ‘compliance’?
  • Implications of fully encoded command bus and DFE in LPDDR5 and DDR5
  • How to send the proper test signals
  • Read/Write eye separation
  • Eye and jitter measurements

Who should attend? Design and validation engineers working to validate and debug DDR in embedded systems.

What attendees will learn? DDR interface basics, the differences between compliance and debug, and best and most efficient practices for DDR probing and test.

Presenter: Mike Engbretson, Product Marketing Manager

Can't attend live? Register anyway, and we will send you the recording and slides afterward.


Want to watch previous sessions?

Part One: Fundamentals of DDR Memory Physical Layer Testing

Register for the rest of the series:
Part Three: Top Tips and Techniques for Better DDR Probing and Testing
Part Four: More Top Tips and Techniques for Better DDR Probing and Testing

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