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Top Tips and Techniques for Better DDR Probing and Testing

Part 3: Become an Expert in DDR Memory Physical Layer Testing Webinar Series

NOW AVAILABLE ON-DEMAND

Top Tips and Techniques for Better DDR Probing and Testing Webinar

How to Become an Expert in DDR Memory Physical Layer Testing Series
Join Teledyne LeCroy for this 4-part DDR Memory Master Class to learn about the basics of DDR testing with oscilloscopes, including common test preparation and challenges, the difference between compliance and debug test tools, and practical tips and techniques to increase your DDR validation efficiency and apply the correct debug tools.

Top Tips and Techniques for Better DDR Probing and Testing
In this session (Part 3), we get specific on how to address real-world probing and connectivity issues that impact DDR3/LPDDR3 and DDR4/LPDDR4 measurement capabilities. We will provide examples of what to do or not do and a pre-compliance test checklist will be reviewed.

Topics to be included:

Example DDR test configurations
Best practices for DDR probing
DDR connectivity with an interposer
Removing resistors when using interposers
Recommendations of what to avoid
DDR probe deskew

Who should attend? Design and validation engineers working to validate and debug DDR in embedded systems.

What attendees will learn? DDR interface basics, the differences between compliance and debug, and best and most efficient practices for DDR probing and test.

Presenter: Mike Hertz, Senior Field Applications Engineer

Watch the rest of the series

Part One: Fundamentals of DDR Memory Physical Layer Testing
Part Two: Beyond DDR Compliance Testing — Using Advanced Debug Tools
Part Four: More Top Tips and Techniques for Better DDR Probing and Testing

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