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DDR Debug Scenarios and Virtual Probing

Part Four of Four

NOW AVAILABLE ON DEMAND

DDR Debug Scenarios and Virtual Probing Webinar

How to Become an Expert in DDR Memory Physical Layer Testing Series
Join Teledyne LeCroy for this 4-part DDR Memory Master Class to learn about the basics of DDR testing with oscilloscopes, including common test preparation and challenges, the difference between compliance and debug test tools, and practical tips and techniques to increase your DDR validation efficiency and apply the correct debug tools.

DDR Debug Scenarios and Virtual Probing
In this session (Part 4), we demonstrate the utility of DDR eye patterns required for testing and debugging DDR3/LPDDR3 and higher speed DDR4/LPDDR4 signals using real-world DDR debug examples and specialized connectivity examples.

Topics to be included:

  • DDR eye pattern formation and jitter
  • Missing clock cycle debug
  • Read and write burst debug
  • Logic, soldering and power supply noise problem debug
  • Virtual probing

Who should attend? Design and validation engineers working to validate and debug DDR in embedded systems.

What attendees will learn? DDR interface basics, the differences between compliance and debug, and best and most efficient practices for DDR probing and test.

Presenter: Mike Hertz, Senior Field Applications Engineer


Want to watch previous sessions?

Part One: Fundamentals of DDR Memory Physical Layer Testing
Part Two: Beyond DDR Compliance Testing — Using Advanced Debug Tools
Part Three: Top Tips and Techniques for Better DDR Probing and Testing

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